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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7531 Group is the 8-bit microcomputer based on the 740 family core technology. The 7531 Group has a serial I/O, 8-bit timers, and an A-D converter, and is useful for control of home electric appliances and office automation equipment.
* Watchdog timer ............................................................ 16-bit 1 * Power source voltage
At 8 MHz XIN oscillation frequency at ceramic oscillation ................................................................................... 4.0 to 5.5 V At 4 MHz XIN oscillation frequency at ceramic oscillation ................................................................................... 2.4 to 5.5 V At 2 MHz XIN oscillation frequency at ceramic oscillation ................................................................................... 2.2 to 5.5 V At 4 MHz XIN oscillation frequency at RC oscillation ................................................................................... 4.0 to 5.5 V At 2 MHz XIN oscillation frequency at RC oscillation ................................................................................... 2.4 to 5.5 V At 1 MHz XIN oscillation frequency at RC oscillation ................................................................................... 2.2 to 5.5 V Power dissipation ............................................ 25 mW (standard) Operating temperature range ................................... -20 to 85 C (-40 to 85 C or -40 to 125 C for extended operating temperature version)
FEATURES
* * * * * * * * * *
Basic machine-language instructions ....................................... 69 The minimum instruction execution time .......................... 0.50 s (at 8 MHz oscillation frequency for the shortest instruction, in highspeed mode) Memory size ROM .............................................. 8K to 16K bytes RAM .............................................. 256 to 384 bytes Programmable I/O ports ........................................................... 29 (25 in 32-pin version) Interrupts .................................................... 12 sources, 8 vectors (11 sources, 8 vectors for 32-pin version) Timers ............................................................................ 8-bit 3 Serial I/O1 ...................................................................... 8-bit 1 (UART) Serial I/O2 ...................................................................... 8-bit 1 (Clock-synchronized) A-D converter ................................................ 10-bit 8 channels (6 channels for 32-pin version) Clock generating circuit ............................................. Built-in type (connect to external ceramic resonator or quartz-crystal oscillator permitting RC oscillation)
* *
APPLICATION
Office automation equipment, factory automation equipment, home electric appliances, consumer electronics, car, etc.
PIN CONFIGURATION (TOP VIEW)
P12/SCLK P13/SDATA P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 VREF RESET CNVSS Vcc XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
P11/TXD P10/RXD P07 P06 P05 P04 P03 P02 P01 P00 P37/INT0 P36(LED6)/INT1 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0)
Package type: 36P2R-A
Fig. 1 Pin configuration (36P2R package type)
M37531M4-XXXFP M37531M4T-XXXFP M37531M8-XXXFP M37531E4FP M37531E8FP
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
24
21
23
20
22
19
P07 P10/RXD P11/TXD P12/SCLK P13/SDATA P14/CNTR0 P20/AN0 P21/AN1
18
17
P06 P05 P04 P03 P02 P01 P00 P37/INT0
25 26 27 28 29 30 31 32
M37531M4-XXXGP M37531M8-XXXGP M37531M4T-XXXGP M37531M4V-XXXGP M37531E4GP M37531E4T-XXXGP M37531E4V-XXXGP
16 15 14 13 12 11 10 9
P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) VSS XOUT XIN
2
1
4
7
5
Package type: 32P6B-A
Fig. 2 Pin configuration (32P6B package type)
P12/SCLK P13/SDATA P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC XIN XOUT VSS
P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC
3
6
8
1 2 3 4 5
32 31 30 29 28
P11/TXD P10/RXD P07 P06 P05 P04 P03 P02 P01 P00 P37/INT0 P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0)
M37531M4-XXXSP M37531M8-XXXSP M37531M4T-XXXSP M37531E4SP M37531E8SP
6 7 8 9 10 11 12 13 14 15 16 16
27 26 25 24 23 22 21 20 19 18 17
Package type: 32P4B
Fig. 3 Pin configuration (32P4B package type)
2
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P14/CNTR0 NC NC P20/AN0 P21/AN1 NC P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 NC NC VREF RESET CNVSS Vcc XIN XOUT VSS
1 2 3 4 5 6 7
42 41 40 39 38 37 36
8 9 10 11 12 13 14 15 16 17 18 19 20 21
35 34 33 32 31 30 29 28 27 26 25 24 23 22
P13/SDATA P12/SCLK P11/TXD P10/RXD P07 P06 P05 P04 P03 P02 P01 P00 NC P37/INT0 P36(LED6)/INT1 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0)
Package type: 42S1M
Fig. 4 Pin configuration (42S1M package type)
M37531RSS
3
12
26 25 24 23 22 21 20 19
11 10 9 8 7 6 5 4
3 2 1 36 35
34 33 32 31 30 29 28 27
VREF
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O port P3
I/O port P2
I/O port P1
I/O port P0
Key-on wake up
4
Reset input VSS VCC
15 13 14 18
FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R)
Clock input RESET CNVSS
Clock output
XIN
XOUT
FUNCTIONAL BLOCK
16
17
Clock generating circuit
CPU
RAM ROM
X Prescaler 12 (8) Prescaler X (8)
CNTR0
A
Timer 1 (8) Timer 2 (8) Timer X (8)
Fig. 5 Functional block diagram (36P2R package)
Y S PC H PS PCL
0
Watchdog timer
Reset
A-D converter (10) SI/O1(8) SI/O2(8)
INT0 INT1
P3(8)
P2(8)
P1(5)
P0(8)
FUNCTIONAL BLOCK DIAGRAM (Package: 32P6B)
Reset input VSS VCC RESET CNVSS
7 6 8 11
Clock input
Clock output
XIN
XOUT
9
10
Clock generating circuit
CPU
RAM ROM
X Prescaler 12 (8) Prescaler X (8)
CNTR0
A
Timer 1 (8) Timer 2 (8) Timer X (8)
5
17 16 15 14 13 12
4 3 2 1 32 31
30 29 28 27 26
25 24 23 22 21 20 19 18
VREF
MITSUBISHI MICROCOMPUTERS
7531 Group
I/O port P3
I/O port P2
I/O port P1
I/O port P0
Key-on wake up
Fig. 6 Functional block diagram (32P6B package)
Y S PC H PS PCL
0
Watchdog timer
Reset
A-D converter (10) SI/O1(8) SI/O1(8)
INT0
P3(6) P2(6)
P1(5)
P0(8)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
5
10
22 21 20 19 18 17
987654
3 2 1 32 31
30 29 28 27 26 25 24 23
VREF
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O port P3
I/O port P2
I/O port P1
I/O port P0
Key-on wake up
6
Reset input VSS VCC RESET CNVSS
12 11 13 16
FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B)
Clock input
Clock output
XIN
XOUT
14
15
Clock generating circuit
CPU
RAM ROM
X Prescaler 12 (8) Prescaler X (8)
CNTR0
A
Timer 1 (8) Timer 2 (8) Timer X (8)
Fig. 7 Functional block diagram (32P4B package)
Y S PC H PS PCL
0
Watchdog timer
Reset
A-D converter (10) SI/O1(8) SI/O2(8)
INT0
P3(6) P2(6)
P1(5)
P0(8)
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description Pin Vcc, Vss VREF CNVss RESET XIN XOUT Name Analog reference voltage CNVss Reset input Clock input Clock output *Reference voltage input pin for A-D converter *Chip operating mode control pin, which is always connected to Vss. *Reset input pin for active "L" *Input and output pins for main clock generating circuit *Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins. *For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor. *If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. P00-P07 I/O port P0 *8-bit I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure *Whether a built-in pull-up resistor is to be used or not can be determined by program. P10/RxD P11/TxD P12/SCLK P13/SDATA P14/CNTR0 P20/AN0- P27/AN7 I/O port P2 (Note 2) I/O port P1 *5-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure *CMOS/TTL level can be switched for P10, P12 and P13 *8-bit I/O port having almost the same function as P0 *CMOS compatible input level *CMOS 3-state output structure P30-P35 I/O port P3 (Note 3) *8-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37). *CMOS 3-state output structure *P30 to P36 can output a large current for driving LED. *Whether a built-in pull-up resistor is to be used or not can be P36/INT1 *Interrupt input pins determined by program. P37/INT0 Notes 1: VCC = 2.4 to 5.5 V for the extended operating temperature version (-40 to 85 C) and the extended operating temperature 125 C version (-40 to 125 C). 2: 6-bit I/O port (P20-P25) for the 32-pin version. 3: 6-bit I/O port (P30-P34, P37/INT0) for the 32-pin version. *Input pins for A-D converter *Timer X function pin *Serial I/O1 function pin *Serial I/O2 function pin *Key-input (key-on wake up interrupt input) pins Function Function expect a port function Power source (Note 1) *Apply voltage of 2.2-5.5 V to Vcc, and 0 V to Vss.
7
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 7531 group as follow: Memory type Support for Mask ROM version, One Time PROM version, and Emulator MCU .
Memory size ROM/PROM size .................................................. 8 K to 16 K bytes RAM size ................................................................ 256 to 384 bytes Package 32P4B ................................................... 32 pin plastic molded SDIP 32P6B-A .................................... 0.8 mm-pitch plastic molded LQFP 36P2R-A .................................. 0.8 mm-pitch plastic molded SSOP 42S1M ..................................... 42 pin shrink ceramic PIGGY BACK
ROM size (Byte)
16K
M37531E8 M37531M8 Under development for M37531M8-XXXSP M37531M4/M4T M37531M4V
8K
M37531E4 M37531E4T/E4V
0
128
256
384
RAM size (Byte)
Note. Products under development: the development schedule and specification may be revised without notice.
Fig. 8 Memory expansion plan Currently supported products are listed below. Table 2 List of supported products Product M37531M4-XXXSP M37531M4T-XXXSP M37531E4SP M37531M4-XXXFP M37531M4T-XXXFP M37531E4FP M37531M4-XXXGP M37531M4T-XXXGP M37531M4V-XXXGP M37531E4GP M37531E4T-XXXGP M37531E4V-XXXGP M37531M8-XXXSP M37531E8SP M37531M8-XXXFP M37531E8FP M37531M8-XXXGP M37531RSS 16384 (16254) 384 32P6B-A 8192 (8062) 256 32P4B (P) ROM size (bytes) RAM size Package ROM size for User () (bytes) Mask ROM version Mask ROM version (extended operating temperature version) One Time PROM version (blank) Mask ROM version 36P2R-A Mask ROM version (extended operating temperature version) One Time PROM version (blank) Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 C version) One Time PROM version (blank) One Time PROM version (shipped after programming, extended operating temperature version) One Time PROM version (shipped after programming, extended operating temperature 125 C version) 32P4B 36P2R-A Mask ROM version One Time PROM version (blank) Mask ROM version One Time PROM version (blank) Remarks
32P6B-A Mask ROM version 42S1M Emulator MCU
8
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
b7 b0
CPU mode register (CPUM: address 003B 16, initial value: 80 16) Processor mode bits b1 b0 0 0 Single-chip mode 01 10 Not available 11
CPU
[CPU Mode Register] CPUM The CPU mode register contains the stack page selection bit. This register is allocated at address 003B16. Switching method of CPU mode register Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method.
Stack page selection bit 0 : 0 page 1 : 1 page
Not used (returns "0" when read) (Do not write "1" to these bits ) Oscillation mode selection bit (Note 1) 0 : Ceramic oscillation 1 : RC oscillation Clock division ratio selection bits b7 b6 0 0 : f() = f(XIN)/2 (High-speed mode) 0 1 : f() = f(XIN)/8 (Middle-speed mode) 1 0 : applied from ring oscillator 1 1 : f() = f(XIN) (Double-speed mode)(Note 2)
Note 1: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. 2: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected.
Fig. 9 Structure of CPU mode register
After releasing reset
Start with a built-in ring oscillator ( Note)
Switch the oscillation mode selection bit (bit 5 of CPUM)
An initial value is set as a ceramic oscillation mode. When it is switched to an RC oscillation, its oscillation starts. Ceramic oscillation: wait time from oscillation start until establishment of oscillation is required. RC oscillation: wait time is not required basically (oscillation is stabilized until the instruction to switch is executed from a ring oscillator.) Switch to other mode except a ring oscillator (Select one of 1/1, 1/2, and 1/8)
Wait until establishment of oscillator clock
Switch the clock division ratio selection bits (bits 6 and 7 of CPUM)
Main routine
Note. After releasing reset the operation starts by starting a ring oscillator automatically. Do not use a ring oscillator at ordinary operation.
Fig. 10 Switching method of CPU mode register
9
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Memory
Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors.
Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
000016 SFR area 004016 010016 Zero page
RAM RAM area
RAM capacity (bytes) address XXXX16
XXXX16 Reserved area 044016 Not used YYYY16 Reserved ROM area
(128 bytes)
256 384
013F16 01BF16
ZZZZ16
ROM ROM area
ROM capacity (bytes) address YYYY16 address ZZZZ16
FF0016
8192 16384
E00016 C00016
E08016 C08016
FFEC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area
Special page
Fig. 11 Memory map diagram
10
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 A-D control register (ADCON) A-D conversion register (low-order) (ADL) A-D conversion register (high-order) (ADH) Serial I/O2 control register (SIO2CON) Serial I/O2 register (SIO2) Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer X mode register (TM) Prescaler X (PREX) Timer X (TX) Timer count source set register (TCSS)
Pull-up control register (PULL) Port P1P3 control register (P1P3C) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG)
003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
Note : Do not access to the SFR area including nothing.
Fig. 12 Memory map of special function register (SFR)
11
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O Ports
[Direction registers] PiD The I/O ports have direction registers which determine the input/output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output. When "1" is set to the bit corresponding to a pin, this pin becomes an output port. When "0" is set to the bit, the pin becomes an input port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating.
[Pull-up control] PULL By setting the pull-up control register (address 001616), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control. [Port P1P3 control] P1P3C By setting the port P1P3 control register (address 001716), a CMOS input level or a TTL input level can be selected for ports P10, P12, P13, P36, and P37 by program.
b7
b0
Pull-up control register (PULL: address 0016 16, initial value: FF 16)
P00 pull-up control bit P01 pull-up control bit P02, P03 pull-up control bit P04 - P07 pull-up control bit P30 - P33 pull-up control bit P34 pull-up control bit P35, P36 pull-up control bit P37 pull-up control bit
Note 1: Pins set to output ports are disconnected from pull-up control. 2: Keep setting the P3 5, P36 pull-up control bit to "1" (initial value) for 32-pin version.
Fig. 13 Structure of pull-up control register
0 : Pull-up Off 1 : Pull-up On
b7
b0
Port P1P3 control register (P1P3C: address 0017 16, initial value: 00 16) P37/INT0 input level selection bit 0 : CMOS level 1 : TTL level P36/INT1 input level selection bit ( Note) 0 : CMOS level 1 : TTL level P10,P12,P13 input level selection bit 0 : CMOS level 1 : TTL level Not used
Note: Keep setting the P3 6/INT1 input level selection bit to "0" (initial value) for 32-pin version.
Fig. 14 Structure of port P1P3 control register
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 5 I/O port function table Pin P00-P07 P10/RxD P11/TxD P12/SCLK P13/SDATA P14/CNTR0 P20/AN0- P27/AN7 P30-P35 P36/INT1 P37/INT0 Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level. 2: The P26/AN6 and P27/AN7 pins do not exist for the 32-pin version. 3: The P35 and P36/INT1 pins do not exist for the 32-pin version. I/O port P2 (Note 2) I/O port P3 (Note 3) External interrupt input Interrupt edge selection register Name I/O port P0 I/O port P1 Input/output I/O individual bits I/O format *CMOS compatible input level *CMOS 3-state output (Note 1) Serial I/O1 function input/output Serial I/O2 function input/output Timer X function input/output A-D conversion input Non-port function Key input interrupt Related SFRs Pull-up control register Serial I/O1 control register Serial I/O2 control register Timer X mode register A-D control register Diagram No. (1) (2) (3) (4) (5) (6) (7) (8) (9)
13
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P0
Pull-up control bit i (i=0 to 3) Direction register
(2) Port P10
Serial I/O1 enable bit (b7) Serial I/O1 enable bit (b6) Receive enable bit Direction register Data bus Port latch
Data bus
Port latch P10,P12,P13 input level selection bit
Serial I/O1 input To key input interrupt generating circuit
(3) Port P11
P11/TxD P-channel output disable bit Serial I/O1 enable bit (b7) Serial I/O1 enable bit (b6) Transmit enable bit Direction register
(4) Port P12
SCLK pin selection bit Direction register
Data bus
Port latch
Data bus
Port latch P10,P12,P13 input level selection bit Serial I/O2 clock output Serial I/O2 clock input
Serial I/O1 output
(5) Port P13
Signals during the SDATA output action SDATA pin selection bit Direction register SDATA pin selection bit
(6) Port P14
Direction register
Data bus
Port latch
Data bus
Port latch
Pulse output mode Timer output P10,P12,P13 input level selection bit Serial I/O2 output Serial I/O2 input CNTR0 interrupt input
P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics.
Fig. 15 Block diagram of ports (1)
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(7) Ports P20 - P27
Direction register
(8) Ports P30 - P35
Pull-up control bit i (i=4 to 6) Direction register
Data bus
Port latch Data bus Port latch
A-D conversion input Analog input pin selection bit
(9) Ports P36, P37
Pull-up control bit i (i=6, 7) Direction register
Data bus
Port latch
P3 input level selection bit
INT interrupt input
P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics.
Fig. 16 Block diagram of ports (2)
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupts
Interrupts occur by 12 different sources : 4 external sources, 7 internal sources and 1 software source. Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to "1" and the interrupt disable flag is set to "0", an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. It becomes usable by switching CNTR0 and AD conversion interrupt sources with bit 7 of the interrupt edge selection register, timer 2 and serial I/O2 interrupt sources with bit 6, timer X and key-on wake-up interrupt sources with bit 5, and serial I/O1 transmit and INT1 interrupt sources with bit 4. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority. Table 6 Interrupt vector address and priority Vector addresses (Note 1) Interrupt source Reset (Note 2) Serial I/O1 receive Serial I/O1 transmit INT1 (Note 3) INT0 Timer X Key-on wake-up Timer 1 Timer 2 Serial I/O2 CNTR0 A-D conversion BRK instruction 9 8 FFEF16 FFEE16 6 7 FFF316 FFF116 FFF216 FFF016 4 5 FFF716 FFF516 FFF616 FFF416 Priority 1 2 3
High-order Low-order
Interrupt operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. Notes on use When the active edge of an external interrupt (INT0, INT1,CNTR0) is set, the interrupt request bit may be set. Therefore, please take following sequence: 1. Disable the external interrupt which is selected. 2. Change the active edge in interrupt edge selection register. (in case of CNTR0: Timer X mode register) 3. Clear the set interrupt request bit to "0". 4. Enable the external interrupt which is selected.
Interrupt request generating conditions At reset input At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or when transmit buffer is empty At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT0 input At timer X underflow At falling of conjunction of input logical level for port P0 (at input) At timer 1 underflow At timer 2 underflow At completion of transmit/receive shift At detection of either rising or falling edge of CNTR0 input At completion of A-D conversion
Remarks Non-maskable Valid when serial I/O1 is selected Valid when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling) STP release timer underflow
FFFD16 FFFB16 FFF916
FFFC16 FFFA16 FFF816
External interrupt (active edge selectable) Non-maskable software interrupt
At BRK instruction execution FFED16 FFEC16 Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: It is an interrupt which can use only for 36 pin version.
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit Interrupt enable bit
Interrupt disable flag I
BRK instruction Reset
Interrupt request
Fig. 17 Interrupt control
b7
b0 Interrupt edge selection register (INTEDGE : address 003A16, initial value: 0016) INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Not used (returns "0" when read) Serial I/O1 or INT1 interrupt selection bit (Do not write "1" for 32 pin version) 0 : Serial I/O1 1 : INT1 Timer X or key-on wake up interrupt selection bit 0 : Timer X 1 : Key-on wake up Timer 2 or serial I/O2 interrupt selection bit 0 : Timer 2 1 : Serial I/O2 CNTR0 or AD converter interrupt selection bit 0 : CNTR0 1 : AD converter
b7
b0 Interrupt request register 1 (IREQ1 : address 003C16, initial value: 0016) Serial I/O1 receive interrupt request bit Serial I/O1 transmit or INT1 interrupt request bit INT0 interrupt request bit Timer X or key-on wake up interrupt request bit Timer 1 interrupt request bit Timer 2 or serial I/O2 interrupt request bit CNTR0 or AD converter interrupt request bit Not used (returns "0" when read)
0 : No interrupt request issued 1 : Interrupt request issued
b7
b0 Interrupt control register 1 (ICON1 : address 003E16, initial value: 0016) Serial I/O1 receive interrupt enable bit Serial I/O1 transmit or INT1 interrupt enable bit INT0 interrupt enable bit Timer X or key-on wake up interrupt enable bit Timer 1 interrupt enable bit Timer 2 or serial I/O2 interrupt enable bit CNTR0 or AD converter interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit)
0 : Interrupts disabled 1 : Interrupts enabled
Fig. 18 Structure of Interrupt-related registers
17
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying "L" level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from "1" to "0". An example of using a key input interrupt is shown in Figure 21, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P00 to P03 as input ports.
Port PXx "L" level output PULL register bit 3 = "0" * P07 output ** Port P07 latch
Falling edge detection
Port P07 Direction register = "1" Key input interrupt request
PULL register bit 3 = "0" * P06 output ** Port P06 latch
Port P06 Direction register = "1"
Falling edge detection
PULL register bit 3 = "0" * P05 output ** Port P05 latch
Port P05 Direction register = "1"
Falling edge detection
PULL register bit 3 = "0" * P04 output ** Port P04 latch
Port P04 Direction register = "1"
Falling edge detection
PULL register bit 2 = "1" * P03 input ** Port P03 latch
Port P03 Direction register = "0"
Falling edge detection
Port P0 Input read circuit
PULL register bit 2 = "1" * P02 input ** Port P02 latch
Port P02 Direction register = "0"
Falling edge detection
PULL register bit 1 = "1" * P01 input ** Port P01 latch
Port P01 Direction register = "0"
Falling edge detection
PULL register bit 0 = "1" * P00 input ** Port P00 latch
Port P00 Direction register = "0"
Falling edge detection
* P-channel transistor for pull-up ** CMOS output buffer
Fig. 19 Connection example when using key input interrupt and port P0 block diagram
18
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timers
The 7531 Group has 3 timers: timer X, timer 1 and timer 2. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches "0", an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to "1".
b7 b0
Timer X mode register (TM : address 002B16, initial value: 0016) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge (in event counter mode) 1 : Interrupt at rising edge Count at falling edge (in event counter mode) Timer X count stop bit 0 : Count start 1 : Count stop Not used (return "0" when read)
qTimer 1, Timer 2
Prescaler 12 always counts f(XIN)/16. Timer 1 and timer 2 always count the prescaler output and periodically sets the interrupt request bit.
qTimer X
Timer X can be selected in one of 4 operating modes by setting the timer X mode register. * Timer Mode The timer counts the signal selected by the timer X count source selection bit. * Pulse Output Mode The timer counts the signal selected by the timer X count source selection bit, and outputs a signal whose polarity is inverted each time the timer value reaches "0", from the CNTR0 pin. When the CNTR0 active edge switch bit is "0", the output of the CNTR0 pin is started with an "H" output. At "1", this output is started with an "L" output. When using a timer in this mode, set the port P14 direction register to output mode. * Event Counter Mode The operation in the event counter mode is the same as that in the timer mode except that the timer counts the input signal from the CNTR0 pin. When the CNTR0 active edge switch bit is "0", the timer counts the rising edge of the CNTR0 pin. When this bit is "1", the timer counts the falling edge of the CNTR0 pin. * Pulse Width Measurement Mode When the CNTR0 active edge switch bit is "0", the timer counts the signal selected by the timer X count source selection bit while the CNTR0 pin is "H". When this bit is "1", the timer counts the signal while the CNTR0 pin is "L". In any mode, the timer count can be stopped by setting the timer X count stop bit to "1". Each time the timer overflows, the interrupt request bit is set.
Fig. 20 Structure of timer X mode register
b7
b0
Timer count source set register (TCSS : address 002E 16, initial value: 0016) Timer X count source selection bit (Note) 0 : f(XIN)/16 1 : f(XIN)/2 Not used (return "0" when read)
Note : To switch the timer X count source selection bit , stop the timer X count operation.
Fig. 21 Timer count source setting register
19
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
f(XIN)/16 f(XIN)/2 Timer X count source selection bit CNTR0 active edge switch bit "0"
Prescaler X latch (8) Pulse width measurement mode Timer mode pulse output mode Prescaler X (8) Event counter mode Timer X count stop bit
Timer X latch (8)
Timer X (8)
To timer X interrupt request bit To CNTR0 interrupt request bit
P14/CNTR0
"1" CNTR0 active edge switch bit "1" Q Q "0" Port P14 latch Port P14 direction register Pulse output mode Toggle flip-flop R T Timer X latch write Pulse output mode
Data bus
Prescaler 12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
f(XIN)/16
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt request bit To timer 1 interrupt request bit
Fig. 22 Block diagram of timer X, timer 1 and timer 2
20
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O qSerial I/O1
Serial I/O1 can be used as an asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation when serial I/O1 is in operation. Eight serial data transfer formats can be selected, and the transfer formats to be used by a transmitter and a receiver must be identical. Each of the transmit and receive shift registers has a buffer register (the same address on memory). Since the shift register cannot be written to or read from directly, transmit data is written to the transmit
Data bus Address (001816) OE
buffer, and receive data is read from the respective buffer registers. These buffer registers can also hold the next data to be transmitted and receive 2-byte receive data in succession. By selecting "1" for continuous transmit valid bit (bit 2 of SIO1CON), continuous transmission of the same data is made possible. This can be used as a simplified PWM.
Serial I/O1 control register Address (001A16) Receive buffer full flag (RBF) Receive interrupt request (RI)
Receive Buffer Register
Character length selection bit P10/RXD ST Detector 7-bit 8-bit PE FE SP Detector Receive Shift Register
1/16 UART Control Register Address (001B16) Clock Control Circuit
BRG count source selection bit XIN 1/4
Division ratio 1/(n+1) Baud Rate Generator Address (001C16) ST/SP/PA Generator 1/16 Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI)
P11/TXD Character length selection bit
Transmit Shift Register
Transmit Buffer Register Continuous transmit valid bit Data bus Address (001816)
Transmit buffer empty flag (TBE) Serial I/O1 status register Address (001916)
Fig. 23 Block diagram of UART serial I/O
Transmit/Receive Clock Transmit Buffer Register Write Signal TBE=0 TSC=0 TBE=1 Serial Output TXD
ST D0
TBE=0 TBE=1
D1 SP ST D0 D1
TSC=1*
SP
Receive Buffer Register Read Signal
1 Start Bit 7 or 8 Data Bit 1 or 0 Parity Bit 1 or 2 Stop Bit
* Generated at second bit in 2-stop -bit mode
RBF=0 RBF=1 Serial Input RXD
ST D0 D1 SP ST D0 D1
RBF=1
SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes "1". 4 : After data is written to the transmit buffer when TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0.
Fig. 24 Operation of UART serial I/O function
21
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Serial I/O1 control register] SIO1CON The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART control register] UARTCON The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P11/TxD pin. [Serial I/O1 status register] SIO1STS The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "11" to bits 7 and 6 of the serial I/O1 control register initializes this register. All bits of the serial I/O1 status register are initialized to "8116" at reset.
[Transmit/Receive buffer register] TB/RB The transmit buffer and the receive buffer are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7-bit, the MSB of data stored in the receive buffer is "0". [Baud Rate Generator] BRG The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
Transmit/Receive Clock Transmit Buffer Register Write Signal TBE=0 TSC=0 TBE=1 Serial Output TXD
ST D0 D1 SP ST D0 D1 SP ST
1 Start Bit 7 or 8 Data Bit 1 or 0 Parity Bit 1 or 2 Stop Bit
Notes 1 : When the serial I/O1 enable bit (b7) is "1", the transmit enable bit is "1", and continuous transmit valid bit is "1", writing on the transmit buffer initiates continuous transmission of the same data. 2 : Select 0 for continuous transmit valid bit to stop continuous transmission. The TXD pin will stop at high level after completing transmission of 1 byte. 3 : If the transmit buffer contents are rewritten during a continuous transmission, transmission of the rewritten data will be started after completing transmission of 1 byte.
Fig. 25 Continuous transmission operation of UART serial I/O
22
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Serial I/O1 status register (SIO1STS: address 001916, initial value: 8116) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE) = 0 1: (OE) U (PE) U (FE) = 1 Not used (returns "1" when read)
Serial I/O1 control register (SIO1CON: address 001A16, initial value: 0216) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Not used (returns "1" when read) Continuous transmit valid bit 0: Continuous transmit invalid 1: Continuous transmit valid Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled b7 b6 0 0 : Serial I/O1 disabled 0 1 : Not available 1 0 : Serial I/O1 enabled 1 1 : Serial I/O1 cleared
b7
b0
UART control register (UARTCON: address 001B16, initial value: E016) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P11/TxD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (returns "1" when read)
Fig. 26 Structure of serial I/O1-related registers (1)
23
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
qSerial I/O2
The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2 the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register. [Serial I/O2 control register] SIO2CON The serial I/O2 control register contains 8 bits which control various serial I/O functions. *Set "0" to bit 3 to receive. *At reception, clear bit 7 to "0" by writing a dummy data to the serial I/ O2 register after completion of shift. *Bit 7 is set to "1" a half cycle (of the shift clock) earlier than completion of shift operation. Accordingly, when using this bit to confirm shift completion, a half cycle or more of the shift clock must pass after confirming that this bit is set to "1", before performing read/ write to the serial I/O2 register.
b7 b0
Serial I/O2 control register (SIO2CON: address 003016, initial value: 0016) Internal synchronous clock selection bits 000 : f(XIN)/8 001 : f(XIN)/16 010 : f(XIN)/32 011 : f(XIN)/64 110 : f(XIN)/128 111 : f(XIN)/256 SDATA pin selection bit (Note) 0 : I/O port / SDATA input 1 : SDATA output Not used (returns "0" when read)
Transfer direction selection bit 0 : LSB first 1 : MSB first SCLK pin selection bit 0 : External clock (SCLK is an input) 1 : Internal clock (SCLK is an output) Transmit / receive shift completion flag 0 : shift in progress 1 : shift completed Note : When using it as a SDATA input, set the port P13 direction register to "0".
Fig. 27 Structure of serial I/O2 control registers
Data bus
1/8 1/16 Divider 1/32 1/64 1/128 1/256
XIN
SCLK pin
selection bit
"1" "0"
Internal synchronous clock selection bits
SCLK
SCLK pin selection bit
"0"
P12/SCLK
"1"
P12 latch Serial I/O counter 2 (3) Serial I/O2 interrupt request
SDATA pin selection bit
"0"
P13/SDATA
"1"
P13 latch
SDATA pin selection bit Serial I/O shift register 2 (8)
Fig. 28 Block diagram of serial I/O2
24
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2 operation By writing to the serial I/O2 register (address 003116) the serial I/O2 counter is set to "7". After writing, the SDATA pin outputs data every time the transfer clock shifts from a high to a low level. And, as the transfer clock shifts from a low to a high, the SDATA pin reads data, and at the same time the contents of the serial I/O2 register are shifted by 1 bit. When the internal clock is selected as the transfer clock source, the following operations execute as the transfer clock counts up to 8. * Serial I/O2 counter is cleared to "0". * Transfer clock stops at an "H" level. * Interrupt request bit is set. * Shift completion flag is set. Also, the SDATA pin is in a high impedance state after the data transfer is complete (refer to Figure 29). When the external clock is selected as the transfer clock source, the interrupt request bit is set as the transfer clock counts up to 8, but external control of the clock is required since it does not stop. Notice that the SDATA pin is not in a high impedance state on the completion of data transfer.
Synchronous clock
Transfer clock
Serial I/O2 register write signal (Note) SDATA at serial I/O2 output transmit SDATA at serial I/O2 input receive D0 D1 D2 D3 D4 D5 D6 D7
Serial I/O2 interrupt request bit set
Note : When the internal clock is selected as the transfer and the direction register of P1 3/SDATA pin is set to the input mode, the SDATA pin is in a high impedance state after the data transfer is completed.
Fig. 29 Serial I/O2 timing (LSB first)
25
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter
The functional blocks of the A-D converter are described below. [A-D conversion register] AD The A-D conversion register is a read-only register that stores the result of A-D conversion. Do not read out this register during an A-D conversion. [A-D control register] ADCON The A-D control register controls the A-D converter. Bit 2 to 0 are analog input pin selection bits. Bit 4 is the AD conversion completion bit. The value of this bit remains at "0" during A-D conversion, and changes to "1" at completion of A-D conversion. A-D conversion is started by setting this bit to "0". [Comparison voltage generator] The comparison voltage generator divides the voltage between VSS and VREF by 1024 by a resistor ladder, and outputs the divided voltages. Since the generator is disconnected from VREF pin and VSS pin, current is not flowing into the resistor ladder. [Channel Selector] The channel selector selects one of ports P27/AN7 to P20/AN0, and inputs the voltage to the comparator. [Comparator and control circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A-D conversion register. When A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Because the comparator is constructed linked to a capacitor, set f(XIN) to 500 kHz or more during A-D conversion.
b7
b0
A-D control register (ADCON : address 003416, initial value: 1016) Analog input pin selection bits 000 : P20/AN0 001 : P21/AN1 010 : P22/AN2 011 : P23/AN3 100 : P24/AN4 101 : P25/AN5 110 : P26/AN6 (Note) 111 : P27/AN7 (Note) Not used (returns "0" when read) AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (returns "0" when read) Note: These can be used only for 36 pin version.
Fig. 30 Structure of A-D control register
Read 8-bit (Read only address 003516) b7 (Address 003516) b9 b8 b7 b6 b5 b4 b3
b0 b2
Read 10-bit (read in order address 003616, 003516) b7 (Address 003616) b7 (Address 003516) b7 b6 b5 b4 b3 b2 b1 b9
b0 b8 b0 b0
Note: High-order 6-bit of address 003616 returns "0" when read.
Fig. 31 Structure of A-D conversion register
Data bus
b7 A-D control register (Address 0034 16) 3 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 A-D control circuit
b0
A-D interrupt request
Channel selector
A-D conversion register (high-order)
Comparator
(Address 0036 16) (Address 0035 16)
A-D conversion register (low-order) 10 Resistor ladder
VREF
Fig. 32 Block diagram of A-D converter
VSS
26
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Watchdog Timer
The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8bit watchdog timer L, being a 16-bit counter. Standard operation of watchdog timer The watchdog timer stops when the watchdog timer control register (address 003916) is not set after reset. Writing an optional value to the watchdog timer control register (address 003916) causes the watchdog timer to start to count down. When the watchdog timer H underflows, an internal reset occurs. Accordingly, it is programmed that the watchdog timer control register (address 003916) can be set before an underflow occurs. When the watchdog timer control register (address 003916) is read, the values of the high-order 6-bit of the watchdog timer H, STP instruction disable bit and watchdog timer H count source selection bit are read. Initial value of watchdog timer By a reset or writing to the watchdog timer control register (address 003916), the watchdog timer H is set to "FF16" and the watchdog timer L is set to "FF16".
Operation of watchdog timer H count source selection bit A watchdog timer H count source can be selected by bit 7 of the watchdog timer control register (address 003916). When this bit is "0", the count source becomes a watchdog timer L underflow signal. The detection time is 131.072 ms at f(XIN)=8 MHz. When this bit is "1", the count source becomes f(XIN)/16. In this case, the detection time is 512 s at f(XIN)=8 MHz. This bit is cleared to "0" after reset. Operation of STP instruction disable bit When the watchdog timer is in operation, the STP instruction can be disabled by bit 6 of the watchdog timer control register (address 003916). When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled, and an internal reset occurs if the STP instruction is executed. Once this bit is set to "1", it cannot be changed to "0" by program. This bit is cleared to "0" after reset.
Data bus Write "FF16" to the watchdog timer control register Watchdog timer L (8) 1/16 Write "FF16" to the watchdog timer control register
"0" "1" Watchdog timer H (8)
XIN
Watchdog timer H count source selection bit STP Instruction Disable Bit STP Instruction Reset circuit Internal reset
RESET
Fig. 33 Block diagram of watchdog timer
b7
b0
Watchdog timer control register (WDTCON: address 0039 16, initial value: 3F 16)
Watchdog timer H (read only for high-order 6-bit) STP instruction disable bit 0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : f(XIN)/16
Fig. 34 Structure of watchdog timer control register
27
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset Circuit
The microcomputer is put into a reset status by holding the RESET pin at the "L" level for the following interval or more according to the power source voltage and XIN is in stable oscillation. After that, this reset status is released by returning the RESET pin to the "H" level. The program starts from the address having the contents of address FFFD16 as high-order address and the contents of address FFFC16 as low-order address. When VCC = 2.2 to 5.5 V, reset input "L" interval is 45 s or more When VCC = 2.4 to 5.5 V, reset input "L" interval is 35 s or more When VCC = 4.0 to 5.5 V, reset input "L" interval is 15 s or more In the case of f() 4 MHz, the reset input voltage must be 0.8 V or less when the power source voltage passes 4.0 V. In the case of f() 2 MHz, the reset input voltage must be 0.48 V or less when the power source voltage passes 2.4 V. In the case of f() 1 MHz, the reset input voltage must be 0.44 V or less when the power source voltage passes 2.2 V.
Poweron Power source voltage 0V Reset input voltage 0V (Note)
RESET
VCC
0.2 VCC
Note : Reset release voltage Vcc = 2.2 V
RESET
VCC Power source voltage detection circuit
Fig. 35 Example of reset circuit
Clock from built-in ring oscillator RESET RESETOUT SYNC Address Data
? ? ? ? ? ? ? ? ? ? FFFC ADL FFFD
ADH,ADL
ADH
Reset address from the vector table
8-13 clock cycles
Notes 1 : A built-in ring oscillator applies about 250 kHz frequency as clock f at average of Vcc = 5 V. 2 : The mark "?" means that the address is changeable depending on the previous state. 3 : These are all internal signals except RESET.
Fig. 36 Timing diagram at reset
28
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 direction register (5) Pull-up control register (6) Port P1P3 control register (7) Serial I/O1 status register (8) Serial I/O1 control register (9) UART control register (10) Prescaler 12 (11) Timer 1 (12) Timer 2 (13) Timer X mode register (14) Prescaler X (15) Timer X (16) Timer count source set register (17) Serial I/O2 control register (18) A-D control register (19) MISRG (20) Watchdog timer control register (21) Interrupt edge selection register (22) CPU mode register (23) Interrupt request register 1 (24) Interrupt control register 1 (25) Processor status register (26) Program counter 000116 000316 000516 000716 001616 001716 001916 001A16 001B16 002816 002916 002A16 002B16 002C16 002D16 002E16 003016 003416 003816 003916 003A16 003B16 003C16 003E16 (PS) (PCH) (PCL)
X 1 0 1 1 X
Register contents
0016 X X 0 0 0 0 0
0016 0016 FF16 0016 0 0 0 0 0 0 1
0216 1 1 0 0 0 0 0
FF16 0116 0016 0016 FF16 FF16 0016 0016 1016 0016 0 1 1 1 1 1 1
0016 0 0 0 0 0 0 0
0016 0016 X X X X 1 X X
Contents of address FFFD16 Contents of address FFFC16
Note X : Undefined
Fig. 37 Internal status of microcomputer at reset
29
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator between XIN and XOUT, and an RC oscillation circuit can be formed by connecting a resistor and a capacitor. Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. Set the constants of the resistor and capacitor when an RC oscillator is used, so that a frequency variation due to LSI variation and resistor and capacitor variations may not exceed the standard input frequency.
qSwitch of ceramic and RC oscillations
After releasing reset the operation starts by starting a built-in ring oscillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register. The bit 5 can be rewritten only once after releasing reset. However, after rewriting it is disable to write any value to the bit.
qDouble-speed mode
When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected.
qOscillation control
* Stop mode When the STP instruction is executed, the internal clock f stops at an "H" level and the XIN oscillator stops. At this time, timer 1 is set to "0116" and prescaler 12 is set to "FF16" when the oscillation stabilization time set bit after release of the STP instruction is "0". On the other hand, timer 1 and prescaler 12 are not set when the above bit is "1". Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(XIN)/16 is forcibly connected to the input of prescaler 12. When an external interrupt is accepted, oscillation is restarted but the internal clock f remains at "H" until timer 1 underflows. As soon as timer 1 underflows, the internal clock f is supplied. This is because when a ceramic oscillator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. So apply an "L" level to the RESET pin while oscillation becomes stable. * Wait mode If the WIT instruction is executed, the internal clock f stops at an "H" level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to "1" before the STP or WIT instruction is executed. When the STP status is released, prescaler 12 and timer 1 will start counting clock which is XIN divided by 16, so set the timer 1 interrupt enable bit to "0" before the STP instruction is executed. Note For use with the oscillation stabilization set bit after release of the STP instruction set to "1", set values in timer 1 and prescaler 12 after fully appreciating the oscillation stabilization time of the oscillator to be used.
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
MISRG(address 003816, initial value: 0016) Oscillation stabilization time set bit after release of the STP instruction 0: Set "0116" in timer1, and "FF16" in prescaler 12 automatically 1: Not set automatically Reserved bits (return "0" when read) (Do not write "1" to these bits) Not used (return "0" when read)
XIN
XOUT
CIN
COUT
Fig. 41 Structure of MISRG
Fig. 38 External circuit of ceramic resonator
XIN
XOUT R C
Fig. 39 External circuit of RC oscillation
XIN
XOUT Open
External oscillation circuit VCC VSS
Fig. 40 External clock input circuit
31
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XIN Rf
XOUT
Main clock division ratio selection bit Middle-speed, High-speed, double -speed mode
1/2
Ring oscillator mode
1/4
1/2
Prescaler 12
Timer 1
Main clock division ratio selection bit Middle-speed mode High-speed mode Double-speed mode Ring oscillator (Note)
Timing (Internal clock)
1/8
Ring oscillator mode
QS R STP instruction WIT instruction
S R
Q
Q
S R STP instruction
Reset Interrupt disable flag l Interrupt request
Note: Ring oscillator is used only for starting.
Fig. 42 Block diagram of internal clock generating circuit (for ceramic resonator)
XOUT
XIN
Main clock division ratio selection bit Middle-speed, High-speed, double -speed mode
1/2
Ring oscillator mode
1/4
1/2
Prescaler 12
Timer 1
Delay
Main clock division ratio selection bit Middle-speed mode High-speed mode Double-speed mode Ring oscillator (Note)
Timing (Internal clock)
1/8
Ring oscillator mode
QS R STP instruction WIT instruction
S R
Q
Q
S R STP instruction
Reset Interrupt disable flag l Interrupt request
Fig. 43 Block diagram of internal clock generating circuit (for RC oscillation)
Note: Ring oscillator is used only for starting.
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is "1". After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock is the same as that of the XIN in double-speed mode, twice the XIN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode.
CPU Mode Register
The oscillation mode selection bit can be rewritten only once after releasing reset. However, after rewriting it is disable to write any value to the bit. When a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. Do not use it when an RC oscillation is selected.
Interrupts
The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction.
NOTES ON USE Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F to 0.1 F is recommended.
Decimal Calculations
* For calculations in decimal notation, set the decimal mode flag D to "1", then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction before the ADC instruction or SBC instruction. * In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid.
Timers
* When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). * When a count source of timer X is switched, stop a count of timer X.
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 k resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor.
Ports
* The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. * Set "1" to each bit 6 of the port P3 direction register and the port P3 register.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is 500kHz or more during A-D conversion. Do not execute the STP instruction during A-D conversion.
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 7 Special programming adapter Package Name of Programming Adapter 32P4B PCA7435SP PCA7435GP PCA7435FP 32P6B-A 36P2R-A
DATA REQUIRED FOR ROM PROGRAMMING ORDERS
The following are necessary when ordering a ROM writing: (1) ROM Programming Confirmation Form (2) Mark Specification Form (for Special Mark) (3) Data to be written to ROM, in EPROM form (three identical copies)
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 44 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150 C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution: The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours.
Fig. 44 Programming and testing of One Time PROM version
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
(1) 7531 Group (General purpose) Applied to: M37531M4-XXXFP/SP/GP, M37531M8-XXXFP/SP/GP, M37531E4FP/SP/GP, M37531E8FP/SP Table 8 Absolute maximum ratings Symbol VCC VI VI VI VO Pd Topr Tstg Power source voltage Input voltage Input voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature P00-P07, P10-P14, P20-P27, P30-P37, VREF RESET, XIN CNVSS (Note 1) P00-P07, P10-P14, P20-P27, P30-P37, XOUT Ta = 25C All voltages are based on VSS. Output transistors are cut off. Parameter Conditions Ratings -0.3 to 7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to 13 -0.3 to VCC + 0.3 300 (Note 2) -20 to 85 -40 to 125 Unit V V V V V mW C C
Note 1: It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version. 2: 200 mW for the 32P6B package product.
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 9 Recommended operating conditions (1) (VCC = 2.2 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC Power source voltage (ceramic) Parameter f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) f(XIN) = 1 MHz (Double-speed mode) Power source voltage (CR) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) f(XIN) = 1 MHz (High-, Middle-speed mode) VSS VREF VIH VIH VIH VIL VIL VIL VIL IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) Power source voltage Analog reference voltage "H" input voltage "H" input voltage (TTL input level selected) "H" input voltage "L" input voltage "L" input voltage (TTL input level selected) "L" input voltage "L" input voltage "H" total peak output current (Note 2) "L" total peak output current (Note 2) "L" total peak output current (Note 2) "H" total average output current (Note 2) "L" total average output current (Note 2) "L" total average output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 P10, P12, P13, P36, P37 (Note 1) RESET, XIN P00-P07, P10-P14, P20-P27, P30-P37 P10, P12, P13, P36, P37 (Note 1) RESET, CNVSS XIN P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 2.0 0.8VCC 2.0 0.8VCC 0 0 0 0 Limits Min. 4.0 2.4 2.2 4.0 2.4 2.2 4.0 2.4 2.2 Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 VCC VCC VCC VCC 0.3VCC 0.8 0.2VCC 0.16VCC -80 80 60 -40 40 30 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Unit V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA
Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 10 Recommended operating conditions (2) (VCC = 2.2 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) "H" peak output current (Note 1) "L" peak output current (Note 1) "L" peak output current (Note 1) "H" average output current (Note 2) "L" average output current (Note 2) "L" average output current (Note 2) Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at RC oscillation Oscillation frequency (Note 3) at RC oscillation Oscillation frequency (Note 3) at RC oscillation Parameter P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 VCC = 4.0 to 5.5 V Double-speed mode VCC = 2.4 to 5.5 V Double-speed mode VCC = 2.2 to 5.5 V Double-speed mode VCC = 4.0 to 5.5 V High-, Middle-speed mode VCC = 2.4 to 5.5 V High-, Middle-speed mode VCC = 2.2 to 5.5 V High-, Middle-speed mode VCC = 4.0 to 5.5 V High-, Middle-speed mode VCC = 2.4 to 5.5 V High-, Middle-speed mode VCC = 2.2 to 5.5 V High-, Middle-speed mode Limits Min. Typ. Max. -10 10 30 -5 5 15 4 2 1 8 4 2 4 2 1 Unit mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz MHz MHz MHz
Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %.
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 11 Electrical characteristics (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VOH Parameter "H" output voltage P00-P07, P10-P14, P20-P27, P30-P37 (Note 1) Test conditions IOH = -5 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 2.2 to 5.5 V VOL "L" output voltage P00-P07, P10-P14, P20-P27, P37 IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.2 to 5.5 V VOL "L" output voltage P30-P36 IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.2 to 5.5 V VT+-VT- VT+-VT- VT+-VT- IIH Hysteresis Hysteresis Hysteresis "H" input current CNTR0, INT0, INT1(Note 2) P00-P07 (Note 3) RXD, SCLK, SDATA (Note 2) RESET P00-P07, P10-P14, P20-P27, P30-P37 RESET XIN P00-P07, P10-P14, P20-P27, P30-P37 RESET, CNVSS XIN P00-P07, P30-P37 VI = VCC (Pin floating. Pull up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors "off") VI = VSS VI = VSS VI = VSS (Pull up transistors "on") When clock stopped High-speed mode, f(XIN) = 8 MHz Output transistors "off" High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V Output transistors "off" Double-speed mode, f(XIN) = 4 MHz Output transistors "off" Middle-speed mode, f(XIN) = 8 MHz Output transistors "off" f(XIN) = 8 MHz (in WIT state) Functions except timers 1 and 2 stop Output transistors "off" f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state) Output transistors "off" Increment when A-D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped (in STP state) Output transistors "off" Ta = 25 C Ta = 85 C 2.0 5.0 0.5 5.0 2.0 1.6 -4.0 -0.2 -0.5 5.5 8.0 1.5 8.0 5.0 3.2 4.0 -5.0 0.4 0.5 0.5 5.0 Limits Min. VCC-1.5 VCC-1.0 1.5 0.3 1.0 2.0 0.3 1.0 Typ. Max. Unit V V V V V V V V V V V A
IIH IIH IIL
"H" input current "H" input current "L" input current
5.0
A A A
IIL IIL IIL VRAM ICC
"L" input current "L" input current "L" input current RAM hold voltage
-5.0
A A mA V mA mA mA mA mA
Power source current
0.2 0.5 0.1 1.0 10
mA mA A A
Notes 1: P11 is measured when the P11/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: RXD, SCLK, SDATA, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to "0" (CMOS level). 3: It is available only when operating key-on wake up.
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 12 A-D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol -- -- -- VOT VFST Resolution Linearity error Differential nonlinear error Zero transition voltage VCC = 2.7 to 5.5 V Ta = 25 C VCC = 2.7 to 5.5 V Ta = 25 C VCC = VREF = 5.12 V VCC = VREF = 3.072 V Full scale transition voltage VCC = VREF = 5.12 V VCC = VREF = 3.072 V tCONV RLADDER IVREF Conversion time Ladder resistor Reference power source input current VREF = 5.0 V VREF = 3.0 V II(AD) A-D port input current 50 30 55 150 70 200 120 5.0 A 0 0 5105 3060 5 3 5115 3069 Parameter Test conditions Limits Min. Typ. Max. 10 3 0.9 20 15 5125 3075 122 Unit Bits LSB LSB mV mV mV mV tc(XIN) k A
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 13 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(SCLK-SDATA) th(SCLK-SDATA) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Parameter Limits Min. 15 125 50 50 200 80 80 1000 400 400 200 200 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns
Table 14 Timing requirements (2) (VCC = 2.2 to 5.5 V or 2.4 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(SCLK-SDATA) th(SCLK-SDATA) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Parameter VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V Limits Min. 45 35 500 250 200 100 200 100 1000 500 460 230 460 230 4000 2000 1900 950 1900 950 400 400 Typ. Max. Unit s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 15 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-SDATA) tv(SCLK-SDATA) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) 10 10 0 30 30 30 30 Limits Min. tC(SCLK)/2-30 tC(SCLK)/2-30 140 Typ. Max. Unit ns ns ns ns ns ns ns ns
Note 1: Pin XOUT is excluded. Table 16 Switching characteristics (2) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-SDATA) tv(SCLK-SDATA) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) 20 20 0 50 50 50 50 Limits Min. tC(SCLK)/2-50 tC(SCLK)/2-50 350 Typ. Max. Unit ns ns ns ns ns ns ns ns
Note 1: Pin XOUT is excluded.
Measured output pin 100 pF
/// CMOS output
Fig. 45 Switching characteristics measurement circuit diagram (General purpose)
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tc(CNTR) twH(CNTR) twL(CNTR) 0.2 VCC
CNTR0
0.8 VCC
twH(CNTR)
twL(CNTR) 0.2 VCC
INT0, INT1
0.8 VCC
tw(RESET)
RESET
0.2 VCC
0.8 VCC
tc(XIN) twH(XIN) twL(XIN) 0.2 VCC
XIN
0.8 VCC
tc(SCLK) tf twL(SCLK) 0.2 VCC tr 0.8 VCC twH(SCLK)
SCLK
tsu(SDATA-SCLK)
th(SCLK-SDATA)
SDATA (at receive)
td(SCLK-SDATA)
0.8 VCC 0.2 VCC tv(SCLK-SDATA)
SDATA (at transmit)
Fig. 46 Timing chart (General purpose)
42
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) 7531 Group (Extended operating temperature version) Applied to: M37531M4T-XXXFP/SP/GP, M37531E4T-XXXGP Table 17 Absolute maximum ratings Parameter Symbol VCC VI VI VI VO Pd Topr Tstg Power source voltage Input voltage Input voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature P00-P07, P10-P14, P20-P27, P30-P37, VREF RESET, XIN CNVSS (Note 1) P00-P07, P10-P14, P20-P27, P30-P37, XOUT Ta = 25C All voltages are based on VSS. Output transistors are cut off.
Conditions
Ratings -0.3 to 7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to 13 -0.3 to VCC + 0.3 300 (Note 2) -40 to 85 -65 to 150
Unit V V V V V mW C C
Notes 1: It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version. 2: 200 mW for the 32P6B package version.
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 18 Recommended operating conditions (1) (VCC = 2.4 to 5.5 V, Ta = -40 to 85 C, unless otherwise noted) Symbol VCC Power source voltage (ceramic) Parameter f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) Power source voltage (CR) VSS VREF VIH VIH VIH VIL VIL VIL VIL IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) Power source voltage Analog reference voltage "H" input voltage "H" input voltage (TTL input level selected) "H" input voltage "L" input voltage "L" input voltage (TTL input level selected) "L" input voltage "L" input voltage "H" total peak output current (Note 2) "L" total peak output current (Note 2) "L" total peak output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 P10, P12, P13, P36, P37 (Note 1) RESET, XIN P00-P07, P10-P14, P20-P27, P30-P37 P10, P12, P13, P36, P37 (Note 1) RESET, CNVSS XIN P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 2.0 0.8VCC 2.0 0.8VCC 0 0 0 0 f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) Limits Min. 4.0 2.4 4.0 2.4 4.0 2.4 Typ. 5.0 5.0 5.0 5.0 5.0 5.0 0 VCC VCC VCC VCC 0.3VCC 0.8 0.2VCC 0.16VCC -80 80 60 -40 40 Max. 5.5 5.5 5.5 5.5 5.5 5.5 Unit V V V V V V V V V V V V V V V mA mA mA mA mA
"H" total average output current P00-P07, P10-P14, P20-P27, P30-P37 (Note 2) "L" total average output current P00-P07, P10-P14, P20-P27, P37 (Note 2)
"L" total average output current P30-P36 mA 30 (Note 2) Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
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MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 19 Recommended operating conditions (2) (VCC = 2.4 to 5.5 V, Ta = -40 to 85 C, unless otherwise noted) Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) "H" peak output current (Note 1) "L" peak output current (Note 1) "L" peak output current (Note 1) "H" average output current (Note 2) "L" average output current (Note 2) "L" average output current (Note 2) Parameter P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 VCC = 4.0 to 5.5 V Double-speed mode VCC = 2.4 to 5.5 V Double-speed mode VCC = 4.0 to 5.5 V High-, Middle-speed mode VCC = 2.4 to 5.5 V High-, Middle-speed mode VCC = 4.0 to 5.5 V High-, Middle-speed mode Limits Min. Typ. Max. -10 10 30 -5 5 15 4 2 8 4 4 2 Unit mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz
Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at RC oscillation
Oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at RC oscillation High-, Middle-speed mode Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %.
45
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 20 Electrical characteristics (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol VOH Parameter "H" output voltage P00-P07, P10-P14, P20-P27, P30-P37 (Note 1) Test conditions IOH = -5 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 2.4 to 5.5 V VOL "L" output voltage P00-P07, P10-P14, P20-P27, P37 IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.4 to 5.5 V VOL "L" output voltage P30-P36 IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.4 to 5.5 V VT+-VT- VT+-VT- VT+-VT- IIH Hysteresis Hysteresis Hysteresis "H" input current CNTR0, INT0, INT1 (Note 2) P00-P07 (Note 3) RXD, SCLK, SDATA (Note 2) RESET P00-P07, P10-P14, P20-P27, P30-P37 RESET XIN P00-P07, P10-P14, P20-P27, P30-P37 RESET, CNVSS XIN P00-P07, P30-P37 VI = VCC (Pin floating. Pull up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors "off") VI = VSS VI = VSS VI = VSS (Pull up transistors "on") When clock stopped High-speed mode, f(XIN) = 8 MHz Output transistors "off" High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors "off" Double-speed mode, f(XIN) = 4 MHz Output transistors "off" Middle-speed mode, f(XIN) = 8 MHz, Output transistors "off" f(XIN) = 8 MHz (in WIT state) Functions except Timer 1 and Timer 2 stop Output transistors "off" f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state) Output transistors "off" Increment when A-D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped (in STP state) Output transistors "off" Ta = 25 C 2.0 5.0 0.5 5.0 2.0 1.6 -4.0 -0.2 -0.5 5.5 8.0 1.5 8.0 5.0 3.2 4.0 -5.0 0.4 0.5 0.5 5.0 Limits Min. VCC-1.5 VCC-1.0 1.5 0.3 1.0 2.0 0.3 1.0 Typ. Max. Unit V V V V V V V V V V V A
IIH IIH IIL
"H" input current "H" input current "L" input current
5.0
A A A
IIL IIL IIL VRAM ICC
"L" input current "L" input current "L" input current RAM hold voltage
-5.0
A A mA V mA mA mA mA mA
Power source current
0.2 0.5 0.1 1.0
mA mA A
A 10 Ta = 85 C Notes 1: P11 is measured when the P11/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: RXD, SCLK, SDATA, INT0 and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to "0" (CMOS level). 3: It is available only when operating key-on wake up.
46
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 21 A-D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol -- -- -- VOT VFST Resolution Linearity error Differential nonlinear error Zero transition voltage VCC = 2.7 to 5.5 V Ta = 25 C VCC = 2.7 to 5.5 V Ta = 25 C VCC = VREF = 5.12 V VCC = VREF = 3.072 V Full scale transition voltage VCC = VREF = 5.12 V VCC = VREF = 3.072 V tCONV RLADDER IVREF Conversion time Ladder resistor Reference power source input current VREF = 5.0 V VREF = 3.0 V II(AD) A-D port input current 50 30 55 150 70 200 120 5.0 A 0 0 5105 3060 5 3 5115 3069 Parameter Test conditions Limits Min. Typ. Max. 10 3 0.9 20 15 5125 3075 122 Unit Bits LSB LSB mV mV mV mV tc(XIN) k A
47
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 22 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(SCLK-SDATA) th(SCLK-SDATA) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1 input "H" pulse width CNTR0, INT0, INT1 input "L" pulse width Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Parameter Limits Min. 15 125 50 50 200 80 80 1000 400 400 200 200 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns
Table 23 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(SCLK-SDATA) th(SCLK-SDATA) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1 input "H" pulse width CNTR0, INT0, INT1 input "L" pulse width Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Parameter Limits Min. 35 250 100 100 500 230 230 2000 950 950 400 400 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns
48
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 24 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-SDATA) tv(SCLK-SDATA) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) 10 10 0 30 30 30 30 Limits Min. tC(SCLK)/2-30 tC(SCLK)/2-30 140 Typ. Max. Unit ns ns ns ns ns ns ns ns
Note 1: Pin XOUT is excluded.
Table 25 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-SDATA) tv(SCLK-SDATA) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) 20 20 0 50 50 50 50 Limits Min. tC(SCLK)/2-50 tC(SCLK)/2-50 350 Typ. Max. Unit ns ns ns ns ns ns ns ns
Note 1: Pin XOUT is excluded.
Measured output pin 100 pF /// CMOS output
Fig. 47 Switching characteristics measurement circuit diagram (Extended operating temperature version)
49
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tc(CNTR) twH(CNTR) twL(CNTR) 0.2 VCC
CNTR0
0.8 VCC
twH(CNTR)
twL(CNTR) 0.2 VCC
INT0, INT1
0.8 VCC
tw(RESET)
RESET
0.2 VCC
0.8 VCC
tc(XIN) twH(XIN) twL(XIN) 0.2 VCC
XIN
0.8 VCC
tc(SCLK) tf twL(SCLK) 0.2 VCC tr 0.8 VCC twH(SCLK)
SCLK
tsu(SDATA-SCLK)
th(SCLK-SDATA)
SDATA (at receive)
td(SCLK-SDATA)
0.8 VCC 0.2 VCC tv(SCLK-SDATA)
SDATA (at transmit)
Fig. 48 Timing chart (Extended operating temperature version)
50
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(3) 7531 Group (Extended operating temperature 125 C version) Applied to: M37531M4V-XXXGP, M37531E4V-XXXGP Table 26 Absolute maximum ratings Parameter Symbol VCC VI VI VI VO Pd Topr Tstg Power source voltage Input voltage Input voltage Input voltage Output voltage Power dissipation Operating temperature (Note 2) Storage temperature P00-P07, P10-P14, P20-P25, P30-P34, P37, VREF RESET, XIN CNVSS (Note 1) P00-P07, P10-P14, P20-P25, P30-P34, P37, XOUT Ta = 25C All voltages are based on VSS. Output transistors are cut off.
Conditions
Ratings -0.3 to 7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to 13 -0.3 to VCC + 0.3 200 -40 to 125 -65 to 150
Unit V V V V V mW C C
Notes 1: It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version. 2: The total time is limited as follows: 6000 hours at 55 to 85 C, 1000 hours at 85 to 125 C
51
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 27 Recommended operating conditions (1) (VCC = 2.4 to 5.5 V, Ta = -40 to 125 C, unless otherwise noted) Symbol VCC Power source voltage (ceramic) Parameter f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) Power source voltage (CR) VSS VREF VIH VIH VIH VIL VIL VIL VIL IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) Power source voltage Analog reference voltage "H" input voltage "H" input voltage (TTL input level selected) "H" input voltage "L" input voltage "L" input voltage (TTL input level selected) "L" input voltage "L" input voltage "H" total peak output current (Note 2) "L" total peak output current (Note 2) "L" total peak output current (Note 2) P00-P07, P10-P14, P20-P25, P30-P34, P37 P10, P12, P13, P37 (Note 1) RESET, XIN P00-P07, P10-P14, P20-P25, P30-P34, P37 P10, P12, P13, P37 (Note 1) RESET, CNVSS XIN P00-P07, P10-P14, P20-P25, P30-P34, P37 P00-P07, P10-P14, P20-P25, P37 P30-P34 2.0 0.8VCC 2.0 0.8VCC 0 0 0 0 f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) Limits Min. 4.0 2.4 4.0 2.4 4.0 2.4 Typ. 5.0 5.0 5.0 5.0 5.0 5.0 0 VCC VCC VCC VCC 0.3VCC 0.8 0.2VCC 0.16VCC -80 80 60 -40 40 Max. 5.5 5.5 5.5 5.5 5.5 5.5 Unit V V V V V V V V V V V V V V V mA mA mA mA mA
"H" total average output current P00-P07, P10-P14, P20-P25, P30-P34, P37 (Note 2) "L" total average output current P00-P07, P10-P14, P20-P25, P37 (Note 2)
"L" total average output current P30-P34 mA 30 (Note 2) Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
52
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 28 Recommended operating conditions (2) (VCC = 2.4 to 5.5 V, Ta = -40 to 125 C, unless otherwise noted) Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) "H" peak output current (Note 1) "L" peak output current (Note 1) "L" peak output current (Note 1) "H" average output current (Note 2) "L" average output current (Note 2) "L" average output current (Note 2) Parameter P00-P07, P10-P14, P20-P25, P30-P34, P37 P00-P07, P10-P14, P20-P25, P37 P30-P34 P00-P07, P10-P14, P20-P25, P30-P34, P37 P00-P07, P10-P14, P20-P25, P37 P30-P34 VCC = 4.0 to 5.5 V Double-speed mode VCC = 2.4 to 5.5 V Double-speed mode VCC = 4.0 to 5.5 V High-, Middle-speed mode VCC = 2.4 to 5.5 V High-, Middle-speed mode VCC = 4.0 to 5.5 V High-, Middle-speed mode Limits Min. Typ. Max. -10 10 30 -5 5 15 4 2 8 4 4 2 Unit mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz
Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at ceramic oscillation or external clock input Oscillation frequency (Note 3) at RC oscillation
Oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at RC oscillation High-, Middle-speed mode Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %.
53
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 29 Electrical characteristics (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Symbol VOH Parameter "H" output voltage P00-P07, P10-P14, P20-P25, P30-P34, P37 (Note 1) Test conditions IOH = -5 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 2.4 to 5.5 V VOL "L" output voltage P00-P07, P10-P14, P20-P25, P37 IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.4 to 5.5 V VOL "L" output voltage P30-P34 IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.4 to 5.5 V VT+-VT- VT+-VT- VT+-VT- IIH Hysteresis Hysteresis Hysteresis "H" input current CNTR0, INT0, (Note 2) P00-P07 (Note 3) RXD, SCLK, SDATA (Note 2) RESET P00-P07, P10-P14, P20-P25, P30-P34, P37 RESET XIN P00-P07, P10-P14, P20-P25, P30-P34, P37 RESET, CNVSS XIN P00-P07, P30-P34, P37 VI = VCC (Pin floating. Pull up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors "off") VI = VSS VI = VSS VI = VSS (Pull up transistors "on") When clock stopped High-speed mode, f(XIN) = 8 MHz Output transistors "off" High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors "off" Double-speed mode, f(XIN) = 4 MHz Output transistors "off" Middle-speed mode, f(XIN) = 8 MHz, Output transistors "off" f(XIN) = 8 MHz (in WIT state) Functions except Timer 1 and Timer 2 stop Output transistors "off" f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state) Output transistors "off" Increment when A-D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped (in STP state) Output transistors "off" Ta = 25 C 2.0 5.0 0.5 5.0 2.0 1.6 -4.0 -0.2 -0.5 5.5 8.0 1.5 8.0 5.0 3.2 4.0 -5.0 0.4 0.5 0.5 5.0 Limits Min. VCC-1.5 VCC-1.0 1.5 0.3 1.0 2.0 0.3 1.0 Typ. Max. Unit V V V V V V V V V V V A
IIH IIH IIL
"H" input current "H" input current "L" input current
5.0
A A A
IIL IIL IIL VRAM ICC
"L" input current "L" input current "L" input current RAM hold voltage
-5.0
A A mA V mA mA mA mA mA
Power source current
0.2 0.5 0.1 1.0
mA mA A
A Ta = 125 C 50 Notes 1: P11 is measured when the P11/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: RXD, SCLK, SDATA, and INT0 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to "0" (CMOS level). 3: It is available only when operating key-on wake up.
54
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 30 A-D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Symbol -- -- -- VOT VFST Resolution Linearity error Differential nonlinear error Zero transition voltage VCC = 2.7 to 5.5 V Ta = 25 C VCC = 2.7 to 5.5 V Ta = 25 C VCC = VREF = 5.12 V VCC = VREF = 3.072 V Full scale transition voltage VCC = VREF = 5.12 V VCC = VREF = 3.072 V tCONV RLADDER IVREF Conversion time Ladder resistor Reference power source input current VREF = 5.0 V VREF = 3.0 V II(AD) A-D port input current 50 30 55 150 70 200 120 5.0 A 0 0 5105 3060 5 3 5115 3069 Parameter Test conditions Limits Min. Typ. Max. 10 3 0.9 20 15 5125 3075 122 Unit Bits LSB LSB mV mV mV mV tc(XIN) k A
55
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 31 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(SCLK-SDATA) th(SCLK-SDATA) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0 input "H" pulse width CNTR0, INT0 input "L" pulse width Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Parameter Limits Min. 15 125 50 50 200 80 80 1000 400 400 200 200 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns
Table 32 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(SCLK-SDATA) th(SCLK-SDATA) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, input "H" pulse width CNTR0, INT0, input "L" pulse width Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Parameter Limits Min. 35 250 100 100 500 230 230 2000 950 950 400 400 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns
56
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 33 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-SDATA) tv(SCLK-SDATA) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) 10 10 0 50 50 50 50 Limits Min. tC(SCLK)/2-50 tC(SCLK)/2-50 200 Typ. Max. Unit ns ns ns ns ns ns ns ns
Note 1: Pin XOUT is excluded.
Table 34 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-SDATA) tv(SCLK-SDATA) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) 20 20 0 80 80 80 80 Limits Min. tC(SCLK)/2-80 tC(SCLK)/2-80 400 Typ. Max. Unit ns ns ns ns ns ns ns ns
Note 1: Pin XOUT is excluded.
Measured output pin 100 pF /// CMOS output
Fig. 49 Switching characteristics measurement circuit diagram (Extended operating temperature 125 C version)
57
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tc(CNTR) twH(CNTR) twL(CNTR) 0.2 VCC
CNTR0
0.8 VCC
twH(CNTR)
twL(CNTR) 0.2 VCC
INT0
0.8 VCC
tw(RESET)
RESET
0.2 VCC
0.8 VCC
tc(XIN) twH(XIN) twL(XIN) 0.2 VCC
XIN
0.8 VCC
tc(SCLK) tf twL(SCLK) 0.2 VCC tr 0.8 VCC twH(SCLK)
SCLK
tsu(SDATA-SCLK)
th(SCLK-SDATA)
SDATA (at receive)
td(SCLK-SDATA)
0.8 VCC 0.2 VCC tv(SCLK-SDATA)
SDATA (at transmit)
Fig. 50 Timing chart (Extended operating temperature 125 C version)
58
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
32P4B
EIAJ Package Code SDIP32-P-400-1.78 JEDEC Code - Weight(g) 2.2 Lead Material Alloy 42/Cu Alloy
Plastic 32pin 400mil SDIP
32
17
1
16
D
Symbol A A1 A2 b b1 b2 c D E e e1 L
e SEATING PLANE
b1
b
b2
Dimension in Millimeters Min Nom Max - - 5.08 0.51 - - - 3.8 - 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 - 1.778 - - 10.16 - 3.0 - - 0 - 15
A
32P6B-A
EIAJ Package Code LQFP32-P-77-0.80 JEDEC Code - Weight(g) Lead Material Alloy 42
L
A1
A2
Plastic 32pin 7!7mm body LQFP
MD
32
25
b2
HD D
e
I2
1 24
Recommended Mount Pad
E HE
Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME
8
17
9
16
A L1 e F
b
A1
y
L Detail F
Dimension in Millimeters Min Nom Max 1.7 - - 0.1 0.2 0 1.4 - - 0.3 0.35 0.45 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 0.8 - - 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 1.0 - - 0.1 - - 0 10 - 0.5 - - 1.0 - - - - 7.4 7.4 - -
A2
c
ME
e1
E
c
59
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
36P2R-A
EIAJ Package Code SSOP36-P-450-0.80 JEDEC Code - Weight(g) 0.53 Lead Material Alloy 42
Plastic 36pin 450mil SSOP
e
36 19
b2
HE
E
F
e1
Recommended Mount Pad Symbol Dimension in Millimeters Min Nom Max 2.4 - - - - 0.05 - 2.0 - 0.5 0.4 0.35 0.2 0.15 0.13 15.2 15.0 14.8 8.6 8.4 8.2 - 0.8 - 12.23 11.93 11.63 0.7 0.5 0.3 - 1.765 - 0.15 - - 0 - 10 - 0.5 - - 11.43 - - - 1.27
1
18
A D A2 A1
L1
e
y
b
A A1 A2 b c D E e HE L L1 y b2 e1 I2
Detail F
60
L
c
I2
MITSUBISHI MICROCOMPUTERS
7531 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
*
* *
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(c) 1999 MITSUBISHI ELECTRIC CORP. New publication, effective Nov. 1999. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
7531 Group DATA SHEET
Rev. date 970822 980220
Rev. Revision Description No. 1.0 First Edition 2.0 Page 1; FEATURES In Programmable I/O ports, the pin number of 32-pin version is added. In Power source voltage, two conditions are added and two are revised. Page 8; Central Processing Unit (CPU) The name of manual, 740 Family Software Manual, is revised. Fig. 11; Note is added. Page 11; [Direction registers] PiD The sentences are revised: Pins set to input are floating, and permit reading pin values. Fig. 12; Bit function and the initial value are added. Fig. 13; The figure name is revised: port P1P3 control register. Page 15; Interrupt operation The order of No. 3 and 4 is revised. Fig. 17; Four bit names are revised: Serial I/O1. Page 21; [Serial I/O1 status register] SIO1STS Explanations are partly revised. Fig. 25; Bits 6 and 7 explanations of serial I/O1 control register are revised. Page 23; [Serial I/O2 control register] SIO2CON Explanations are partly revised. Fig. 26; Bit 3 explanations are revised. Note is partly revised. Page 27; Reset Circuit Explanations are partly revised: In the case of f(f)... Fig. 35; The waveform of clock from built-in ring oscillator is revised. Note 1 is revised. Fig. 36; (6) Port P1P3 control register is added. Page 32; A-D Converter Explanations are partly revised: The WIT instruction is eliminated. Page 33; DATA REQUIRED FOR ROM PROGRAMMING ORDERS This clause is added. Table 7; Characteristics of Vcc is revised. Table 8; Characteristics of f(XIN) is revised. Table 9; Characteristics of Icc is revised. Table 12; Characteristics of tC(XIN), tWH(XIN), tWL(XIN), tC(CNTR), tWH(CNTR), tWL(CNTR), tC(SCLK), tWH(SCLK) and tWL(SCLK) are revised. Pages 42 to 45; MASK ROM CONFIRMATION FORM These are added. Pages 46 and 47; ROM PROGRAMMING CONFIRMATION FORM These are added.
(1/3)
REVISION DESCRIPTION LIST
7531 Group DATA SHEET
Rev. date 980220
Rev. Revision Description No. 2.0 Pages 48 to 51; MARK SPECIFICATION FORM These are added. Pages 52 and 53; PACKAGE OUTLINE These are added. 2.1 Pages 37, 46, 47; Some words are corrected. Pages 42 to 47; The numbers of Mask ROM and ROM Programming Confirmation Forms are revised. Page 49; 32P6B Mark Specification Form is revised. 3.0 All pages; "PRELIMINARY Notice: This is ... " eliminated. All register structures; Initial values are added. Page 1; Explanations are partly revised. Page 1 and 2; Product names are added into the pin configurations. Page 3; Pin configuration of 42S1M is added. Page 8; Explanations of Figure 8 and Table 2 are partly revised. Page 9; Explanations of Figures 9 and 10 are partly revised. Page 11; The register name (Timer count souce set register) is revised. Page 16; Table 4; The contents of "Remarks" is partly revised. Page 20; Explanation is revised. Page 21; The some word is added. Page 24; The some word is added. Explanation is revised. Page 26; Explanation is added. Page 27; Figure 34; Explanation is revised. Page 28; Period is added. Page 32; Figure titles of Figures 42 and 43 are revised. Page 33; Explanation is revised. Page 36 to 59; "ELECTRICAL CHARACTERISTICS" are all revised. "ELECTRICAL CHARACTERISTICS" of Extended operating temperature version is added. "ELECTRICAL CHARACTERISTICS" of Extended operating temperature 125 C version is added. Page 60 to 71; "MASK ROM CONFIRMATION FORM" and "ROM PROGRAMMING CONFIRMATION FORM" are all revised. "SHRINK DIP MARK SPECIFICATION FORM" eliminated. 4.0 Most of the contents (Functional Description, Electrical characteristics, and so on) are updated.
980702
990212
991115
(2/3)
REVISION DESCRIPTION LIST
7531 Group DATA SHEET
Rev. date 000615
Rev. Revision Description No. 4.1 Page 1: Power dissipation to 25 mW Operating temperature range; Note deleted Page 8: Fig. 8 "Under development" revised Page 10: Fig.11 Start address of Interrupt vector area to FFEC16 Page 25: Fig.29 Note revised Page 28: Description revised; RESET "L" pulse width 2 s 15 s Page 32: Fig.42 Rd resistor connected to XOUT pin eliminated Page 39: Table 12 Absolute accuracy (excluding quantization error) Linearity error Page 40: Table 13 tw(RESET) revised; 2 s 15 s Table 14 tw(RESET) revised; 2 s 45 s at VCC = 2.2 to 5.5 V, 35 s at VCC = 2.4 to 5.5 V Page 47: Table 21 Absolute accuracy (excluding quantization error) Linearity error Page 48: Table 22 tw(RESET) revised; 2 s 15 s Table 23 tw(RESET) revised; 2 s 35 s Page 55: Table 30 Absolute accuracy (excluding quantization error) Linearity error Page 56: Table 31 tw(RESET) revised; 2 s 15 s Table 32 tw(RESET) revised; 2 s 35 s 4.2 Pages 28, 32: Character fonts errors revised
000905
(3/3)

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